For decades, the tech world had a simple rule of thumb: if you want a faster, more efficient computer chip, you just make the transistors smaller. But as silicon hits its physical limits and making things smaller gets incredibly expensive, that old rule—known as Moore’s Law—is running out of steam. To tackle this head-on, Huawei just introduced a completely different approach that shifts the focus from physical size to something else entirely: time.
Speaking at the 2026 IEEE International Symposium on Circuits and Systems (ISCAS), Huawei’s He Tingbo laid out this new vision in a keynote titled “New Semiconductor Path in Practice.” The star of the show was the “Tau (τ) Scaling Law.” Instead of obsessing over geometric scaling—shrinking the physical dimensions of a chip—Huawei is proposing that the industry focus on time (τ) scaling. In plain English, the goal is to steadily boost transistor density and system speed by aggressively compressing the time it takes for signals to travel through a piece of silicon.
To make this happen, Huawei isn’t just tweaking one part of the chip; they’ve built a coordinated strategy that works from the ground up. At the very bottom, engineers are fine-tuning the physical transistors to reduce resistance and unwanted capacitance, clearing out tiny data traffic jams before they start. Just above that, at the circuit level, they’ve introduced a clever layout architecture called “LogicFolding.” This technique throws out traditional chip layout boundaries to drastically shorten internal wiring, cutting down the electrical drag that slows down signals.
Higher up the tech stack, Huawei is blending software, hardware architecture, and silicon together. This full-stack design gives the system ultra-precise control over how data and instructions flow, allowing for massive parallel processing and faster execution times. Finally, for large-scale data centers and AI setups, they’ve rolled out a new interconnect protocol called UnifiedBus. This allows massive computing clusters to share memory natively, practically eliminating the communication lag that usually slows down giant networks.
If this sounds like a futuristic research project, Huawei notes that it is already a proven reality. Over the last six years, the company has quietly designed and mass-produced 381 different chips using these exact Tau Scaling principles across various industries.
The big test for everyday consumers is happening very soon. Huawei confirmed that its upcoming Kirin smartphone chips, dropping in Fall 2026, will be the very first commercial products to feature the LogicFolding architecture to supercharge performance. Looking further down the road, Huawei predicts that by 2031, its high-end chips using Tau Scaling will reach a transistor density equivalent to a cutting-edge 14 A˚ (1.4 nm) process.
Ultimately, Huawei acknowledges that rewriting the rules of semiconductors isn’t a solo job. He Tingbo closed the keynote by inviting scientists, engineers, and tech partners from all over the world to collaborate on the Tau Scaling framework, arguing that open teamwork is the only way to keep pushing the boundaries of global computing power.
